1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to an improved SRAM design for stable SRAM performance and reduced power consumption.
2. Description of the Related Art
Historically, as circuit feature sizes are reduced and supply voltages are lowered, it has become increasingly difficult to achieve stable SRAM performance and design an SRAM cell that has both adequate static noise margin (SNM) and adequate trip voltage (Vtrip). The trip voltage (Vtrip) is a measure of the ability of a cell to write digital data into a SRAM cell.
The SNM quantifies the amount of voltage noise required at the internal nodes of the SRAM cell to flip the state of the digital data stored in the SRAM cell. The SNM may be determined graphically by plotting the voltage transfer curve of one of the inverters that comprises the latch of the SRAM cell and inverting the transfer curve of the other inverter. The voltage difference between the two voltage transfer curves is the SNM.
For SRAM cells in general, SNM and Vtrip are interdependent and design techniques that improve SNM, tend to degrade Vtrip and vice-versa. For example, if the passgate transistor is too strong relative to the drive transistor, SNM is degraded. If the pass gate is too weak relative to the drive transistor, Vtrip is degraded. The SNM can be improved by decreasing the voltage on the bitline, which weakens the passgate transistor. The SNM improves linearly with decreasing bitline voltage until the bitline voltage is about equal to the threshold voltage of the passgate transistor. Thus, SRAM design has become a delicate balance of the relative strengths of the passgate, drive, and load transistors.
It is within this context that embodiments of the claimed invention arise.